Summer 2025 #cvut defended theses by OTREES/my students:

• Matyáš Bobek, FlexCAN Controller Emulation for QEMU, #qemu #canbus (git), I hope for mainlining soon, my thanks to
  @marckleinebudde for review
• Albert Bezděk, Stereo Camera FPGA Interface and Processing for Zynq Based Systems, with initial rectification and disparity in #XilinX #Zynq #FPGA (git), thank to Martin Meloun for review
• Michal Matiáš, NuttX RTOS Driver for Single Unshielded Twisted Pair Communication, working with ncv7410 and ESP32-C6 for now (nuttx, apps git), continues by #GSoC expected to lead to broader OpenAlliance SPI Ethernet MAC-PHY T1S for mainline #NuttX support after summer, thanks to @cynerd for review

See the last OTREES theses list for link to repositories and more

Another related theses from #cvut Faculty of Information Technologies mentored by Michal Štepanovský to mention:

• Jan Medek, Implementation of RISC-V soft-core processor on FPGA board with real-time operating system support, port (git) of #NuttX to the own setup of Ibex #riscv to Digilent Basys 3 and Digilent Nexys Video, includes even #NuttX, #RTEMS, #Zephyr, #FreeRTOS and RT-Thread choice analysis, some minor clarifications in my review, out of the text documentation, the student ported NuttX even to the CPU system prepared in frame of the next thesis
• Ondřej Golasowski, RISC-V open-source microarchitecture analysis and optimization, the VESP-BETA single-cycle RV32IMZicsr #riscv design for basic #comparch education with #FPGA labs

Stay tuned next summer as well, there is student interesting in thesis to add MMU to #QtRvSim

There are #Framework13 models now with #AMD CPUs! This is getting interesting for many reasons!

1. The AMD Ryzen AI CPUs come with a #NPU based on #XDNA from the #Xilinx acquisition. In practice #AMDXDNA only made it into Linux 6.14 (e.g. in the very recent Fedora 42) and there is no end user support as of today making the NPU dead hardware as of today and probably most of 2025.

2. The AMD Ryzen CPUs come with AVX512 and that's working end to end unlike whatever the f #Intel is doing there.

#FPGA dorks. I'm running into an issue where #vivado says: multiple drivers on MMCM pins when I use a known good block (LVDS deserializer from appnote xapp523) in the vivado block diagram for a 7 series #xilinx #zynq part (snickerdoodle black). I get the error even if I pin out directly to top level pins. I hate using the gui because it hides too much magic. Has anyone hit this madness before?

I'm trying to deserialize a 1.024 Mbps 8b10b lvds to get it on the linux side for storage on disk.

AMD NPU and Xilinx Versal AI Engines Signal Processing in Radio Astronomy (2024) [pdf]

https://git.astron.nl/RD/acap/-/raw/main/Presentation_FPL24_Vincent_Sprave.pdf

#HackerNews #AMD #NPU #Xilinx #Versal #AI #Radio #Astronomy #Signal #Processing #2024

PCIe Endpoint on Xilinx 7-Series FPGAs with PCIe_2_1 Hard Block and GTP

https://github.com/regymm/pcie_7x

#AMD Moves Up Instinct #MI350/#MI355X To Now Release By Mid-2025, #MI400 Lineup Slated For 2026 As #Datacenter Biz Hits Records
Last year the datacenter business at AMD, which includes #EPYC #CPU, Instinct #GPU, #Pensando #DPU, and #Xilinx #FPGA accelerators, accounted for $12.58 billion in sales, or 48.8% of revenues. In both Q3 and Q4 of 2024, datacenter drove in excess of half of AMD’s revenues and nearly 60% of its operating income.
https://www.nextplatform.com/2025/02/04/amd-moves-up-instinct-355x-launch-as-datacenter-biz-hits-records/

Et voici un #AtariST un peu étrange ! C'est une carte MicroPhase Z7-Lite avec un SoC #Xilinx Zynq (un processeur #ARM + un #FPGA), avec le logiciel ZeST de @zerkman à l'intérieur !
La partie matérielle d'un #Atari STF y est décrite en VHDL et tourne dans le FPGA (y compris le processeur 68000). Clavier/souris sont en USB et la vidéo en HDMI.
On peut mettre des images de disquettes et de disques dur sur la carte SD, il y a un petit Linux dans l'ARM qui permet de rendre visible le contenu des fichiers à la partie "silicium" contenue dans le FPGA (si j'ai bien compris le principe).
C'est très chouette tout ça :-)

The Bubble Bobble arcade core is now working on #Xilinx #FPGA s on the #MiSTeX #retrogaming platform.
Thanks to the great work of @somhi (on GitHub) , this port only took 10 minutes.

The 1943 core is now working on #Xilinx #FPGA s on the #MiSTeX #retrogaming platform.
Thanks to the great work of @somhi (on GitHub) , this port only took 30 minutes.

The 1942 core is now working on #Xilinx #FPGAs on the #MiSTeX #retrogaming platform.
Thanks to the fantastic work of @somhi (on GitHub),
I could write a shell script which automates most of the gruntwork of the porting process.
This is the first one ported with that script.
I did the script and this port in a couple of hours.

Long-shot to end all long-shots but: does anybody know anything about USB on raw Xilinx transceivers (e.g. without a PHY)? Officially it's unsupported, occasionally people say they've gotten it to work and more details on exactly how would be incredibly useful

Boosts appreciated for visibility
#openhardware #hardware #xilinx

AMD Embedded: Xilinx bestimmt die Bühne während der Rest herunterfällt https://www.computerbase.de/2024-04/amd-embedded-xilinx-bestimmt-die-buehne-waehrend-der-rest-herunterfaellt/ #AMD #xilinx #ew24

This week's work. Implement dynamic reconfiguration core for #Xilinx #FPGAs. Integrate into #MiSTeX #opensource #retrogames #console. Now changing video modes and #HDMI works with Xilinx FPGAs for the first time. Up to 1366x768@60. FullHD not yet. Hope for the new board revision.
VGA works with 1080p.

Does anyone have manuals for Xilinx X-ACT 2.12? I'm getting close to having a developer workstation for XC2064 FPGAs put together. Before I exhibit it, I want to have some familiarity with entering a design, building it, and loading it into a dev board.

Any #uboot (the #bootloader) experts here? I’m trying to boot a #PetaLinux image, but I get

Verifying Hash Integrity ... sha256 error!
Bad hash value for 'hash-1' hash node in 'ramdisk-1' image node
Bad Data Hash
Ramdisk image is corrupt or invalid
Booting using Fit image failed

even though when I extract the image (no matter whether with dd or dumpimage), the resulting SHA256 _does_ match the checksum listed in the #FIT. What’s going on?

Booo, #Xilinx. #PetaLinux #bashism

Help! My Service-Manual invents new vendors Oo #xilinx

Preissteigerungen: AMDs erhöht Xilinx' FPGA-Preise um bis zu 25 Prozent https://www.computerbase.de/2022-11/preissteigerungen-amds-erhoeht-xilinx-fpga-preise-um-bis-zu-25-prozent/ #AMD #Xilinx